In recent years, information processing systems with the information processing device and a plurality of memories coupled in series have been proposed to cope with ever higher data transfer speeds at higher operating frequencies, as well as to reduce the number of signals between the information processing device and the memory as shown in patent document 1. More specifically, each of the memories contains a request queue to retain requests sent from the information processing device, and a response queue to retain responses to the information processing device. The response queue includes response queues for retaining responses from its own memory and response queues for retaining responses from post-stage memories. An internal arbiter circuit functions to mediate the responses retained in these response queues, and sends the responses to the first stage of the memory and the information processing device.